High Performance DFT Implementation Engineer
hace 5 días
We are seeking a highly skilled High Performance DFT Implementation Engineer to join our Xeon and Networking Engineering (XNE) team at Intel. As an integral part of our SoC design process, you will be responsible for implementing advanced Design-for-Test (DFT) capabilities on state-of-the-art silicon designs.
Key Responsibilities- Develop SoC Test Implementation plans describing strategies to address DFT requirements for designs
- Plan hierarchical test architectures, insert DFT structures, and generate test patterns for logic verification and HVM ATE testing
- Collaborate with the Static Timing Analysis team for timing closure in DFT modes and support the Test Engineering team during silicon bring-up and New Product Introduction
- SoC Design-for-Test principles including SCAN for logic testing, BIST and repair for memory test, JTAG Boundary SCAN
- DFT architecture development and planning for an SoC
- Test insertion, test pattern generation, simulation, and validation
- Industry-standard DFT tools such as Mentor Graphics Tessent, Synopsys DFT Compiler, DFTMax, TetraMax
- Static Timing Analysis, Synopsys PrimeTime, constraints, and timing path debug
- Scripting languages like PERL, TCL/Tk, Python
- Intermediate English level, verbal & written
- Knowledge of manufacturing tester capabilities, Automatic Test Equipment (ATE), and test program experience
- Knowledge of DFT integration of IP (e.g. DDR, SerDes, PLL's) into an SoC
This salary range is based on national averages in the United States and may vary depending on location, experience, and other factors. We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock, bonuses, health, retirement, and vacation benefits.
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