Silicon Test Implementation Specialist
hace 1 semana
About Intel
">Xeon and Networking Engineering (XNE) is a business group at Intel that focuses on the development and integration of Xeon and Networking SOC's and critical IP's to sustain Intel's Xeon and 5G networking roadmap.
">Job Title: Silicon Test Implementation Specialist
">The estimated salary for this position is $145,000 per year.
">Job Description:
">The Design-for-Test (DFT) Implementation Engineer is responsible for implementing DFT capabilities on state-of-the-art silicon designs. This challenging and cutting-edge position involves working with both external tier-1 customers and internal product design teams during their ASIC design cycle.
">You will be responsible for developing the SoC Test Implementation plan describing strategies to address DFT requirements, planning hierarchical test architectures, inserting DFT structures, generating and validating test patterns, supporting STA teams for timing closure, and collaborating with the Test Methodology team and IP development teams.
">Required Skills and Qualifications:
">- ">
- DFT principles including SCAN for logic testing, BIST and repair for memory test, JTAG Boundary SCAN">
- DFT architecture development and planning for an SoC">
- Test insertion, test pattern generation, simulation, and validation using industry-standard tools like Mentor Graphics Tessent, Synopsys DFT Compiler, DFTMax, TetraMax">
- Intermediate English level, verbal & written">
Benefits:
">This role offers a total compensation package consisting of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation.
">Working Model:
">This position is eligible for Intel's hybrid work model allowing employees to split their time between working on-site at their assigned Intel site and off-site.
">Intel's Hybrid Work Model
">This role requires collaboration with internal teams and customers, thus, some on-site presence may be required.
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