Digital Design Engineer
hace 3 semanas
Job Summary:
We are seeking a highly skilled Digital Design Engineer to join our team at Intel. As a key member of our design team, you will be responsible for developing logic design, register transfer level (RTL) coding, simulation, and providing design for test (DFT) timing closure support. You will also participate in the definition of architecture and microarchitecture features of the block, subsystem, and system-on-chip (SoC) under DFT being designed.
Key Responsibilities:
Develop HVM content for rapid bring-up and ramp to production on automatic test equipment (ATE). Apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimize logic to qualify the design to meet power, performance, area, timing, test coverage, defect per million (DPM), and test time/vectormemory reduction goals. Review the verification plan and drive verification of the DFT design to achieve desired architecture and microarchitecture specifications.
Qualifications:
Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical, or Computer Engineering, or equivalent. At least 2 years of experience in Unix/Linux and shell programming. At least 2 years of experience with DFT and knowledge. Advanced English level. Costa Rican unrestricted work permit.
Preferred Qualifications:
DFT tools and techniques, digital design fundamentals, logic/RTL design, formal equivalence verification (FEV), MCO/timing/clock exceptions, SoC clocking, static timing analysis, test content development, and experience in writing and producing software code using TCL.
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