Digital Logic Design Engineer
hace 1 mes
As a Digital Logic Design Engineer at Intel, you will be responsible for developing the logic design, register transfer level (RTL) coding, and simulation for an SoC design. You will integrate the logic of IP blocks and subsystems into a full chip SoC or discrete component design. You will participate in the definition of architecture and microarchitecture features of the block being designed. You will perform quality checks in various logic design aspects ranging from RTL to timing/power convergence. You will apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. You will review the verification plan and implementation to ensure design features are verified correctly and resolve and implement corrective measures for failing RTL tests to ensure correctness of features. You will follow secure development practices to address the security threat model and security objects within the design. You will work with IP providers to integrate and validate IPs at the SoC level. You will drive quality assurance compliance for smooth IP to SoC handoff.
Key Responsibilities:
- Develops logic design, RTL coding, and simulation for SoC design.
- Integrates logic of IP blocks and subsystems into full chip SoC or discrete component design.
- Participates in definition of architecture and microarchitecture features of block being designed.
- Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
- Applies strategies, tools, and methods to write RTL and optimize logic.
- Reviews verification plan and implementation to ensure design features are verified correctly.
- Follows secure development practices to address security threat model and security objects within design.
- Works with IP providers to integrate and validate IPs at SoC level.
- Drives quality assurance compliance for smooth IP to SoC handoff.
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Senior Digital Logic Design Engineer
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