Senior Chip Design Expert

hace 1 día


San José, San José, Costa Rica Screenovate A tiempo completo

**Job Overview**

Screenovate is seeking a highly skilled Full Chip Engineer to join our team of innovative professionals. This role will be responsible for developing timing and power methodologies, executing full-chip timing for Intel's Programmable Solutions Group's next generation product lines in the world's most advanced process technologies.

**About Us**

As part of Intel, Screenovate's Programmable Solutions Group (PSG) combines Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities. Our group is committed to creating an energetic and dynamic work environment that is driven by ingenuity and innovation.

**Key Responsibilities**

Design and Architecture understanding including interaction with Front End and Back End teams, clocking and constraints development, understanding extraction issues, design margins, timing signoff, and quality checks.

Collaborate with cross-functional teams to define system level power optimization solutions, provide power targets to design teams, and commit product power to meet business goals.

Be part of debug and troubleshooting for a wide variety of tasks up to and including difficult, critical design issues and proactive intervention.

**Requirements**

8+ years of relevant experience should include:

Experience in SoC development, 32nm and below process nodes, industry standard timing formats such as Liberty, Verilog, and Design Constraints (SDC), Static Timing Analysis (STA), Correlating STA results with Spice, Timing modeling, library QA, Power analysis tools like Primetime-PX, Redhawk, Power Artist, and Spice.

Script writing for design automation in one or more of the following languages (Python, Perl, or TCL), Silicon modeling concepts (e.g., AOCV, POCV).

**Preferred Qualifications**

10+ years of SoC Development/Timing Lead Experience, experience in completion of several complex multi-voltage domain designs, power model generation, low-power strategy, common modes of operation, functional, and DFT for constraint review and management.

**What We Offer**

A hybrid work model allowing employees to split their time between working on-site at their assigned Intel site and off-site. Annual salary range for jobs which could be performed in US, California: $156,410.00-$250,410.00, salary range dependent on factors including location and experience.



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