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Verification Engineer Position

hace 2 semanas

San José, San José, Costa Rica Siemens Digital Industries Software A tiempo completo

About the Role

This exciting new Verification Engineer position within the Design Verification Technologies Group at Siemens Digital Industries Software reports to the Technical Product Manager for the Design Verification Technology division.

You will join a strong team that is rapidly growing its business in a fast-growing market segment. The role involves developing and maintaining SystemVerilog models or components within those models, writing test cases/compliance test cases to verify functionality of customer DUTs and the VIP itself, analyzing simulation reports and debugging failures in both internal regressions and customer reported issues.

Key Responsibilities

  • Develop and maintain SystemVerilog models or components within those models
  • Write testcases/compliance testcases to verify functionality of customer DUTs and the VIP itself
  • Analyze simulation reports and debug failures in both internal regressions and customer reported issues

Requirements

  • Bachelor's degree or master's degree in Electrical or Computer Engineering
  • Must possess excellent problem solving and debug skills
  • Experience in developing SystemVerilog / UVM based testbenches
  • Experience in working with industry standard protocols like AXI, USB, PCIe or others
  • Strong background on functional verification fundamentals, like environment planning, test plan generation, environment development
  • Experience in using industry standard simulation and debug tools like QuestaPrime, VCS, Xcellium simulators, Verdi, DVE, etc.

About Siemens Digital Industries Software

Siemens Digital Industries Software automates verification and debug of complex SoCs and FPGAs, dramatically increasing productivity and helping companies manage resources more efficiently. Our best-in-class technologies maximize the effectiveness of verification at the block, subsystem, and system levels.