Senior Memory System Verification Engineer

hace 2 días

San José, Costa Rica Screenovate A tiempo completo

As a Memory Controller and IO Sub-system Verification Technical Lead, you will lead the team from specification to product, including Tech Readiness, verification test bench and test strategy, reviews, firmware and Design for Excellence (DFX) verification enablement.
You will be the face of the organization to drive verification of memory controller with interface to all design domains.
In this position, your responsibilities will include, but not be limited to:

- Define verification strategy for high performance and low power DDR I/O controller and highly configurable IO Sub-system.
DDR technologies spans from DDR4, DDR5, LPDDR4 and LPDDR5.
- Architect and Develop pre-silicon verification OVM/UVM based environment/test-bench and test sequences.
- Evaluate and develop Bus Functional Models (BFMs) to interface with the IP with the capability of monitoring transaction and checking protocol.
- Define verification strategies, methodologies and write complete test plans.
- Develop testcases, assertions and functional coverage using System Verilog.
- Setup and run GLS to verify the asynchronous and multi-cycle paths.
- Debug test failures and implement corrective measures for the failing conditions.
- Analyze and drive functional coverage.
- Develop automated tools or scripts for pre-silicon verification efficiency improvement.
- Collaborate with SOC/Sub-system on IP integration issues.
- Collaborate closely with micro-architects and logic/analog designers.
- Brings a strong technical background in micro-architecture design, logic and verification methodology.
- Passionate about working in a dynamic environment where the expectation is to contribute in any activity that makes the business successful.
**Qualifications** Education Requirement**
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
**Minimum Qualifications**
8+ years of experience of:

- OVM or UVM verification methodologies.
- Experience in using verification tools (e.g., VCS, DVE, Verdi, ModelSim, etc.)
- DDR4 or DDR5 architecture and pre-silicon DDR debug/IO PHY training.
**Preferred Qualifications**
- Experience in JEDEC specification, DDR architecture LP 4/5, BFMs/VIPs.
- Experience with verifying memory controller for DDR4/5.
- Coding experience that includes logic and behavioral modelling SV coding.
- Experience in Formal Property Verification method.
- Experience in High Speed I/O Design and Mixed signal design.
- Hardware description language (Verilog and assertion coding) and logic simulation experience.
- Experience in IP integration is an added advantage.
- Experience in power aware design, UPF, multi-power domain checks.
- Experience solving, debugging various simulation failures, and formal verification.
- Experience with post-silicon DDR debug and IO PHY training.
**Inside this Business Group**
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera.
As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today.
Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency.
PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation.
We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees.
That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
**Covid Statement**

**Posting Statement**
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
**Benefits**

**Working Model**
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
**In certain circumstances the work model may change to accommodate business needs.

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