High-Performance GPU Architect

hace 7 horas


San José, San José, Costa Rica Intel A tiempo completo

At Intel, our Xe Structural Design (XSD) silicon development team is innovating in ASIC implementation and verification of multimillion gate designs in advanced process nodes across multiple foundries. We are passionate about delivering best-in-class visual experiences that enable users to immerse themselves in a new visual future.

In this role as a Graphics HW Physical Design Engineer, you will be part of a world-class IP physical design team developing groundbreaking high-performance GPU IPs for high-end graphics, gaming, artificial intelligence, media processing, and more.

This is a great opportunity to join a talented team focused on accelerating high-performance computing and graphics solutions. Your responsibilities may include:

  • Developing physical design implementation and verification flows as well as optimization capabilities for multiple IP blocks
  • Optimization for improving product-level parameters such as power, frequency, and area
  • Verification and signoff ranging from static timing analysis, formal verification, reliability, power crossings, and layout verification

To succeed in this position, you should have a Bachelor's Degree in Electrical/Electronics/Computer Engineering or a directly related discipline with 6+ years of experience in one or more of the following areas:

  • Proven experience in signoff domains (Timing/Quality/Extraction/Reliability/Formal Equivalence Verification)
  • ASIC physical design implementation and tape out
  • Demonstrated problem-solving in ASIC implementation
  • Automation skills through Unix, Linux, Perl, TCL, and Python programming

We value fluency in written and spoken English (Advanced Level). Preferred skills and experience include:

  • Master's degree in Electrical/Electronics/Computer Engineering
  • Proficiency with industry-standard EDA tools: Design Complier, Genus, FC, Innovus, Primetime, Tempus, Spyglass, RedHawk, LEC Formality, Conformal, etc.
  • Power performance area (PPA) optimization through logic-design and EDA tool options
  • CAD flow development and methodology definition for APR Auto Place and Route on leading technologies
  • Graphics architecture experience, logic design, and microarchitecture

This role will be eligible for our hybrid work model allowing employees to split their time between working on-site at their assigned Intel site and off-site.



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