Structured Asic Fabric Configuration Architect
hace 3 días
In this position you will be responsible for architecting and leading the development of the Structured ASIC Fabric Configuration Firmware to minimize the initialization time and enable all the device features.
This role requires expert knowledge in the following areas: NIOS Architecture and FW Development, Emulation Platforms, High-Speed Memory Interface Configuration and High-Speed Interconnect Bus Architectures.
**Responsibilities will include, but are not limited to**:
- Architect the configuration flow for the Structured ASIC Fabric optimizing the initialization time and the communication with the other Subsystems.
- Define the firmware development environment and create an end-to-end solution for integrating the Fabric data with the main subsystem.
- Define the firmware verification plan and drive the implementation of the required testcases with the front-end and post-silicon validation teams.
- Work with the HW Emulation Team to identify additional areas of coverage which are difficult to achieve through standard Verification methodologies.
- Define the configuration flow for high-speed memory interfaces which are requiring training using embedded NIOS CPUs.
- Architect the fabric configuration debugging methodology using JTAG to collect data from all the initialization stages.
- Define the DFT configuration flow allowing initialization with custom data required to exercise the chip under all conditions.
- Excellent written and verbal communication skills, both technical and nontechnical, with public speaking experience.
- Passion to exceed expectations and constantly push the envelope.
- Experience translating complex business and technical challenges into technical solutions.
- Debugging skills.
- Highly motivated self-starter, able to work in a collaborative environment with cross-organizational teams as well as independently
**Qualifications**
Bachelor's Degree in Computer Science, Computer Engineering or Computational Science plus 9 or more years of industry work experience, or
Master's Degree in in Computer Science, Computer Engineering or Computational Science and 6+ years of work experience.
**Minimum Qualifications**:
- 8+ years of experience in Chip Design.
- 8+ years of experience in NIOS Architecture and Embedded SW Development.
- 8 years of experience in Advanced knowledge of Emulation Platform based testing.
- 7 years of experience in Firmware Development.
- 7 years of experience with HDL languages like Verilog and System Verilog.
- 7 years of experience with one or more scripting languages like Python, TCL or PERL.
- 7 years of experience with Debug Interfaces (mainly JTAG) is considered a big plus.
**Inside this Business Group**
The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
**Covid Statement**
**Posting Statement**
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
**Benefits**
**Working Model**
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
**In certain circumstances the work model may change to accommodate business needs.
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