Mixed Signal DFT Expert
hace 2 semanas
Design for Testability
At Intel, we're committed to delivering high-quality products on time. To achieve this, we need to ensure that our integrated circuits are testable and manufacturable. That's where our Design for Testability (DFT) comes in.
About the Role
We're seeking a Senior Analog Dv/Hvm Engineer to join our team. As a key member of our IPSG, you will be responsible for developing DFT implementations, performing pre-silicon verification of functional and structural test content, and enabling and executing test content on automated test equipment platforms.
You will work in an environment where design and documentation are done concurrently with test development activities. Your responsibilities will include ensuring the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp.
You will make significant contributions to design, development, and validation of testability circuits. This will involve evaluation, development, and debug of complex test methods, as well as developing and debugging complex software programs to convert design validation vectors and drive complex test equipment.
You will also create and test validation and production test hardware solutions, test, validate, modify, and redesign circuits to guarantee component margin to specification, analyze and evaluate component specification versus performance to ensure optimal match of component requirements with production equipment capability, with specific emphasis on yield analysis and bin split capability.
Furthermore, you will analyze early customer returns with emphasis on driving test hole closure activities, create and apply concepts for optimizing component production relative to both quality and cost constraints, and autonomously plan and schedule your own daily tasks, developing solutions to problems utilizing formal education and judgment.
What We Offer
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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